The statements in this section merely provide background information related to the present disclosure and may not constitute prior art.
Various DC-DC converters are being used in power supplies. These converters includes buck derived topologies (such as forward converters and bridge converter), or boost derived topologies (such as a flyback converter), or multi-stage converters. One example of a multi-stage DC-DC converter is a two-stage buck-fed full-bridge converter which includes a buck converter as the first stage, and an open-loop DC-DC converter (such as full-bridge converter or an interleaved resonant converter) as the second stage.
For example, a typical buck converter employs an inductor at the output of a switching transistor placed between an energy source, such as a battery or other DC source, and the inductor of a switching transistor. A diode is typically coupled to the inductor/switching transistor interconnection. As the switching transistor is turned on and off under the control of a pulse width modulator, the inductor is energized with a current, thus storing energy in the inductor. When the switching transistor is turned off, current continues to flow through the inductor, discharging the energy stored in the inductor. Typically, a capacitor is placed across the output of the converter to hold the converter output voltage at a predetermined level during the periods when the switching transistor is charging the inductor. A buck converter operates in continuous mode if the current through the inductor remaining above zero during the commutation or discharge cycle. A buck converter operates in discontinuous mode if current though the inductor reaches zero for a period of time. DC-DC converters, especially when designed to work in a continuous mode of operation, tend to shift in operation between continuous mode and discontinuous mode during the transition from full load to light load condition.
If power consumption on a power supply varies widely over a short period of time, this greatly complicates power distribution which in turn increases the total cost of the system. Variation of power consumption, called step load, is the difference between maximum and minimum power consumption of the system.
Step loads applied to a power supply are desirably minimized because the change in current of the step load can be orders of magnitude faster than the typical reaction time of the power supply which results in a drop in output voltage. When designing a DC-DC converter, one of the many considerations is to meet the step load requirement when the converter is operating in both continuous and discontinuous mode, because the closed-loop bandwidth decreases greatly when the converter transitions from continuous mode to discontinuous mode.
One factor which limits the speed with which the converter responds to load variations is the size of the output filter inductor. The rate of change of current through the inductor is inversely related to the inductance. Thus, one way to improve the converter response time is to decrease the size of the output inductor. However, as the inductance is decreased, the inductor will operate in discontinuous mode at even higher loads. In order to maintain a continuous mode operation, the frequency at which the power switch operates generally increases, thereby increasing switching losses.
Another way to reduce the drop in output voltage is to increase the size of the output capacitor. The larger the output capacitor, the more charge stored and available for accommodating varying load requirements. However, cost and size considerations limit the feasibility of increasing the size of the output capacitor.
A converter can be controlled either in voltage mode or current mode. In a voltage mode controlled converter, the voltage appearing at the load is sensed by an error amplifier through a voltage divider network. The error amplifier generates an error voltage which is related to the voltage appearing at the output of the converter. Relatively small changes in voltage appearing at the output of the converter appears as relatively large voltage swings at the output of the error amplifier. As will be described in greater detail, the output of the error amplifier is coupled to one terminal of a comparator which has another terminal coupled to a fixed frequency ramp signal. As the voltage appearing at the output of the error amplifier varies respect to the ramp signal voltage, the output of the comparator changes state in a pulse width modulated waveform. This signal is coupled to the switching transistor to effect the switching thereof and complete a regulator loop.
In a current mode converter, a peak current detection scheme is typically employed in the generation of the pulse width modulated drive signal. Specifically, a sense resistor is placed in series with the switching transistor and inductor. The series resistor senses the current flow in the inductor. The switching transistor is typically controlled by a flip/flop having an output that varies in accordance with a clock signal having a predetermined frequency. Whenever the output of the flip-flop is high, the switching transistor turns on. When the switching transistor is turned on, current flow will begin to build in the inductor. The voltage appearing across the current sensing resistor is coupled to a comparator which is compared to an error voltage similar the one generated in voltage mode operation. As the voltage appearing across the sense resistor rises above the error voltage level, the output of the comparator changes state and resets the flip/flop, thereby turning off the switching transistor until the next clock cycle. Thus, in a current mode converter, the inductor charging cycle is initiated by a fixed frequency clock signal and is terminated once the peak inductor current reaches the error voltage level. The rate at which the current flow changes during an inductor charging cycle is referred to as the slope of the current waveform. It has been found that converters typically operate in reliable and stable manner when a ramp waveform signal is summed with the sensed current waveform.
Two-stage converters have become attractive for high input voltage and low output voltage/high output current applications. The converters typically include a buck converter in the first stage. The second stage converter is typically one of a push-pull, half-bridge, forward, and full-bridge converter design. Two-stage converters have several desirable characteristics. For example, synchronous rectification in the second stage can be optimized to use lower voltage rated MOSFETs since the transformer secondary voltage is minimized. Another characteristic is that the transformer primary voltage in the second stage is reduced and regulated by the first stage buck converter. This allows the efficiency of the second stage to be increased over single-stage design by using lower Rds(on) MOSFETs for the primary side switches.
Two-stage converters also have some disadvantages. For example, two-stage converters generally use only one control loop to regulate the output voltage. Since both the first stage and the second stage include LC filters, the control transfer function becomes 4th order and control system design challenges increase. Conventional compensations can be used to stabilize the two-stage converter, but the dynamic response typically declines. When the two-stage converter operates with a high voltage input, such as 400V, the use of synchronous rectification in the first stage becomes less practical. Without synchronous rectification the buck converter behavior changes at light load. This further complicates the control system design. Adjusting the converter response is especially difficult for multi-stage converters, partially because of the L-C filter in the second stage converter.
Synchronous rectifiers can be employed at the buck stage to force the converter to operate in continuous mode for the complete load range. Referring now to FIG. 1, a first type of prior art two-stage converter 100 is shown. A first stage 102 includes a buck converter that feeds a DC-DC converter second stage 104. First stage 102 includes a DC supply 106. In some embodiments, DC supply 106 provides between 300V and 400V. A positive terminal of DC supply 106 connects to a drain of a FET Q1 and one end of a capacitor C1. A negative terminal of DC supply 106 connects to a ground 108 and one end of a load sensing resistor RS. A first inductor L1 connects between a source of FET Q1 and the other end of capacitor C1. A drain of a FET Q2 connects to a source of FET Q1. A source of FET Q2 connects to the other end of load sensing resistor RS.
A buck control circuit 110 provides a first gate drive signal 112 to a gate of FET Q1 and a second gate drive signal 114 to a gate of FET Q2. Buck control circuit 110 generates first and second gate drive signals 112, 114 based on a load feedback signal 116 that is generated across load sensing resistor RS. An output voltage of first stage 102 is generated across capacitor C1.
Second stage 104 is a full bridge DC-DC converter. A source of a FET Q3 connects to a drain of a FET Q5 and to a first terminal 120 of a transformer T1. A source of FET Q4 connects to a drain of FET Q6 and a second terminal 122 of transformer T1. Second stage 104 receives power from the output of first stage 102. The input voltage positive node, which appears at the top of capacitor C1, connects to drains of FET Q3 and FET Q4. The input voltage negative node, which appears at the bottom of capacitor C1, connects to sources of FET Q5 and FET Q6. A full bridge open loop controller 122 generates gate signals that are applied to respective gates of FETs Q3-Q6.
Transformer T1 includes a center-tapped secondary winding. The secondary winding includes a first terminal 130, a second terminal 132 and a center tap 134. A rectifier D1 has an anode connected to first terminal 130 and a cathode connected to a first end of a second inductor L2. A rectifier D2 has an anode connected to second terminal 132 and a cathode connected to the cathode of rectifier D1 and the first end of second inductor L2. The other end of inductor L2 connects to one end of a capacitor C2. The other end of capacitor C2 connects to center tap 134. The output voltage of two-stage converter 100 is generated across capacitor C2.
Buck control circuit 110 receives a feedback signal 140 that is based on the output voltage across capacitor C2. The feedback signal arrives at buck control circuit 110 through a feedback path that includes a compensation circuit 150 and an opto-isolator 152. The output voltage across capacitor C2 is applied to a first end of a capacitor C3 and one end of a resistor R1. The other end of capacitor C3 connects to a first end of a resistor R2. The second ends of resistors R1 and R2 are connected together and also connected to one end of a resistor R3 and an inverting input 154 of an operational amplifier 156. The other end of resistor R3 connects to ground 108. A non-inverting input of operational amplifier 156 receives a reference voltage from a secondary DC supply 159. The secondary DC supply 159 is referenced to ground 108. An output 160 of operational amplifier 156 connects to inverting input 154 through a capacitor C4 connected in parallel with a series combination of a resistor R4 and a capacitor C5. Output 160 also connects to a first end of a resistor R5. The other end of resistor R5 connects to an anode of opto-isolator 152. A cathode of opto-isolator 152 connects to ground 108. The feedback signal 140 is generated by an open-collector output of opto-isolator 152. An emitter of the open collector transistor connects to ground 108.
Referring now to FIG. 2 a second type of prior art two-stage converter 200 is shown. Two-stage converter 200 is identical to two-stage converter 100 with the exception of having a first stage 202 that includes a buck-converter of an alternate construction. First stage 202 receives power from DC supply 106. The positive terminal of DC supply 106 connects to a cathode of a rectifier D4 and to one end of a capacitor C10. The other end of capacitor C10 connects to one end of an inductor L3. The other end of inductor L3 connects to an anode of rectifier D4 and a drain of a FET Q10. A source of FET Q10 connects to one end of load sensing resistor RS. A second end of load sensing resistor RS connects to ground 108 and the negative terminal of DC supply 106. An output voltage of first stage 202 is generated across capacitor C10 and applied to the full bridge rectifier of second stage 104.
A buck control circuit 204 receives a sensed inductor current signal 206 that is generated across load sensing resistor RS. Buck control circuit 204 uses a peak current mode control scheme that is implemented with a first integrated circuit U1. In some embodiments, U1 includes a UC3842 device available from Fairchild Semiconductor. Buck control circuit 204 generates a gate drive signal 208 that is applied to a gate of FET Q10 through a resistor R12. The other end of resistor R12 connects to pin 6 of integrated circuit U1. A secondary supply voltage 210 is referenced to ground 108 and connects to pin 7 of integrated circuit U1. The feedback signal 104 from opto-isolator 152 connects to one end of a resistor R14 and to pin 1 of integrated circuit U1. The other end of resistor R14 connects to pin 8 of integrated circuit U1 and to one end of a resistor R16. The other end of resistor R16 connects to one end of a resistor R17, one end of a capacitor C11, and pin 4 of integrated circuit U1. The other end of capacitor C11 connects to ground 108. A capacitor C12 connects between pin 3 of integrated circuit U1 and ground 108. pins 2 and 5 of integrated circuit U1 connect to ground 108. The sensed inductor current signal 206 connects to one end of a resistor R18. The other end of resistor R18 connects to the other end of resistor R17, the other end of capacitor C12, and pin 3 of integrated circuit U1. Integrated circuit U1 generates a ramp waveform at pin 4. The ramp waveform is added to the sensed inductor current signal 206 through resistor R17 and generates the gate drive signal from FET Q10 at pin 6 of integrated circuit U1.
The statements in this section merely provide background information related to the present disclosure and may not constitute prior art.